--
-- VHDL Architecture vga_lib.pixel_clock.arch
--
-- Created:
--          by - andax656.student (southfork-12.edu.isy.liu.se)
--          at - 10:19:29 10/05/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY pixel_clock IS
   PORT( 
      vga_clk      : BUFFER std_logic;
      fpga_clk     : IN     std_logic;
      fpga_reset_n : IN     std_logic
   );

-- Declarations

END pixel_clock ;

--
ARCHITECTURE arch OF pixel_clock IS
BEGIN
  process(fpga_clk)
    variable cnt : std_logic := '0';
  begin
    if rising_edge(fpga_clk) then
      if(fpga_reset_n = '0') then
        cnt := '0';
      else
        cnt := not cnt;
        if(cnt = '1') then
          vga_clk <= not vga_clk;
        end if;
      end if;
    end if;
  end process;
END ARCHITECTURE arch;

